The rivals unfurled details of their next server chips at the International Solid State Circuits Conference taking place in San Francisco this week and each took a slightly different tack.
With Tulsa, a dual-core Xeon server chip from Intel coming in the second half of the year, the emphasis tips toward performance. The chip will run at 3.4GHz, faster than the 3GHz Xeon chip (formerly code-named Paxville) on the market today. Tulsa also comes with a 16MB unified cache, a large reservoir of memory on the chip for rapid data access. This means that each of the cores can access data from the entire cache. Presently, Intel and AMD dual-core chips sport segregated caches; dual-core chips from IBM come with a unified cache.
This change increases performance on some applications by up to 10 percent, said Nimish Modi, vice president of the Digital Enterprise Group at Intel. The chip will also be the first from Intel to incorporate Pellston, a virtualisation technology that allows the chip to run multiple operating systems.
Tulsa will also contain energy conservation technology. The cache memory can go into sleep and deep sleep modes that can save up to 6 watts of energy consumption. In current chips, the cache remains on most of the time and inadvertently leaks electricity, which increases power consumption.
"The bulk of the power consumption in cache is through leakage," Modi said.
Still, Tulsa sports a thermal design power (or thermal ceiling) of 150 watts. That's lower than Paxville, which comes with a 165-watt TDP. Chips usually don't hit their thermal ceilings, but server manufacturers have to compensate for it in their designs. A high thermal ceiling can also translate to a high average power consumption.
By contrast, the Pacifica chip coming from AMD has a 95-watt thermal ceiling and will come with AMD's own virtualisation technology, according to the company.
The two 512KB caches on Pacifica are also dedicated to the two cores. AMD won't have a unified cache until next year, according to the road map on the company's site.
"The two 512KB caches on Pacifica are also dedicated to the two cores."
The '512KB' is wrong.
All AMD server chips have 1MB L2 cache per core.