The strains of creating faster processors will get an airing among chipmakers this week.
Researchers and design engineers from IBM and Intel will present papers at the International Electron Devices Meeting (IEDM) that detail their work on "strained silicon," a manufacturing technique that promises to boost processor performance by up to 20 percent.
The San Francisco convention, one of the principal events for semiconductor designers, will feature a keynote speech by Intel Chairman Andy Grove as well as presentations from Sony, Samsung, Pennsylvania State University and the Massachusetts Institute of Technology, among others.
Strained silicon--like double-gate and triple-gate transistors, silicon on insulator (SOI) and other new design ideas coming to the fore--should allow chipmakers to maintain the performance curve established by Moore's Law, the semiconductor industry principle stating that manufacturers will double the number of transistors on chips every two years.
Typically, increasing the number of transistors (a trick accomplished by shrinking them) leads to higher performance and new capabilities for processors. But this approach also leads to escalating levels of energy consumption, among other problems--spurring designers to come up with creative solutions.
"There is a fundamental change in the methodology of progress," said Bernard Meyerson, chief technology officer of IBM's Technology group, which includes IBM Microelectronics. "You are going to work a hell of a lot harder to stay on a predictive curve...You are actually going to have to increase the innovation in materials."
This change in perspective means that deep research in materials and transistor design--especially the kind of research that IBM and Intel researchers specialise in--will become much more important in the future. The concept of strained silicon has been around for 30 years, but it only recently moved to the center of concern for chip designers.
Strained silicon--which will appear in Intel's Prescott chip next year--stretches the distances between the silicon atoms in transistors, the tiny on/off switches that form the basis of a chip.
Moving these atoms slightly farther apart reduces the atomic forces that interfere with the movement of electrons through the transistors, leading to better performance and lower energy consumption for the chip.
In strained silicon, the atoms are stretched by inserting germanium atoms into the chip's silicon lattice. Another chipmaking technique involves adding a layer of silicon-germanium into the transistor bed. The two technologies are conceptually related--but different--and can be used in the same chip.
Intel's Grove is expected to touch on some of the hurdles facing chip designers during an IEDM keynote address scheduled for Tuesday. The speech is expected to cover the semiconductor industry's approach to past problems and its future challenges, including the use of new materials and the introduction of new transistor designs, an Intel representative said.
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